The present disclosure relates generally to control circuits and methods adapted for switched mode power supplies, and more particularly to control circuits and methods regarding to over voltage protection in switched mode power supplies.
Power converters are always needed in most electronic devices, to provide adequate power with specific voltage or current that electronic devices require for proper operation. To protect those powering or powered from being damaged by fault operation conditions, most power converters are designed to equip with protection mechanisms, such as over-load protection (OLP), over-temperature protection (OTP), output-short protection (OSP), over-voltage protection (OVP), and the like.
When a feedback loop of a power converter that, to regulate an output voltage, detects the condition of an output voltage is broken, the power converter might mistakenly interpret the output voltage is too low and continue raising its output power, causing the output voltage to rise accordingly. OVP could stop the output voltage from being over high, and prevent those powered by the output voltage from being over stressed.
FIG. 1 illustrates a conventional power converter 8, including flyback topology 10, operation voltage supply 12, and power controller 18. Operation voltage supply 12 provides operation voltage Vcc at node VCC, powering power controller 18, which might be in the form of a monolithic integrated circuit. Power converter 8 regulates output voltage VOUT at output node OUT to supply power to load 20.
When a feedback loop that detects the condition of output voltage VOUT at output node OUT is broken, output voltage VOUT might start to increase steadily. Due to the inductive coupling, operation voltage VCC provided by operation voltage supply 12 increases as well. It can be designed that when operation voltage VCC is determined to be over high power controller 18 stops the power conversion provided by power converter 8, such that OVP is achieved.
FIG. 2 exemplifies power controller 18 including oscillator 40, pulse-width modulator 44, OVP control circuit 30, and gate logic 42. Oscillator 40 provides clocks that power controller needs for timing. Pulse-width modulator 44 determines the duty cycle, the ON time of power switch 15 in proportion of a cycle time. OVP control circuit 30 prepares power-good signal SPG to inform gate logic 42 whether operation voltage VCC is good. Gate logic 42 controls power switch 15 via gate node GATE.
FIG. 3A shows operation voltage VCC and power-good signal SpPS about the time when OVP is triggered due to a broken feedback loop. At the beginning of FIG. 3A, operation voltage VCC is out of regulation and continues to rise. At time point t1 when operation voltage VCC exceeds over-voltage reference VREF-OVP, comparator 34 resets SR flip flop 32, power-good signal SPG is deasserted to be “0” in logic, such that gate logic 42 deems operation voltage VCC to be not good and keeps power switch 15 OFF accordingly, stopping the following power conversion. Thus, OVP is triggered.
As the power conversion is stopped, operation voltage VCC starts to decline because that power controller 18 is alive and consumes the power from operation voltage VCC. It might be designed that when operation voltage VCC is lower than reference voltage VREF-RSTRT power conversion is restarted or resumed to raise both output voltage VOUT and operation voltage VCC. Nevertheless, power-good signal SPG is kept as being “0” in logic until time point t2. As shown in FIG. 3A, at time point t2, operation voltage VCC exceeds reference voltage VREF-UV, comparator 36 and single-pulse generator 38 switch power-good signal SPG to be “1” in logic, and gate logic 42 deems operation voltage VCC good from now on. Hold-time THOLD) represents the time period when power conversion is paused or stopped.
FIG. 3B shows operation voltage VCC and power-good signal SPS about the time when OVP is triggered due to voltage noise temporarily occurring at operation voltage node VCC. As shown in FIG. 3B, operation voltage VCC soars at about time point t3 because, for some reasons, voltage noise suddenly occurs at operation voltage node VCC. At time point t3, operation voltage VCC exceeds over-voltage reference VREF-OVP, and OVP is triggered. Even though voltage noise subsides soon and operation voltage VCC quickly goes back to its normal value, operation voltage VCC cannot be deemed to be good until operation voltage VCC experiences the similar event sequences shown in FIG. 3A. Namely, operation voltage VCC will decline to reference voltage VREF-RSTRT and then rise to reference voltage VREF-UV, as shown in FIG. 3B, such that power-good signal SPG becomes “1” in logic at time point t4. As shown in FIG. 3B, hold-time THOLD is considerably long.